In a non-volatile semiconductor memory device, for instance, in the case of a NAND flash memory device, it is effective to detect and correct bit errors by ECC (Error Checking and Correcting) to guarantee sufficient reliability of the non-volatile semiconductor memory device. For instance, in a standard non-volatile memory system for a multi-value NAND flash memory device, an ECC is equipped which allows modification and correction of 4 symbols of bit errors per one page.
As one of the technologies to detect the bit errors, a “bit scan method” has been applied. The “bit scan method” is a method to detect whether all the memory cells are in a predetermined data holding state by performing a short batch processing. For instance, by using the “bit scan method”, a non-volatile semiconductor memory device providing a detection circuit is proposed in which the method can detect whether all the memory cells are in the predetermined data holding state by performing batch processing at a short time, and further can detect not only whether the whole result of read-out for verification is passed but also can detect a number of failures (bit errors) with a high speed, (U.S. Pat. No. 6,507,518).
In a non-volatile semiconductor memory device, it is advantageous for cost reduction that reliability is guaranteed and the numbers of failures (bit errors) are allowed to the extent that it is allowed to correct with the aforementioned ECC, even though the whole result of the read-out for verification is not passed. A function which has been developed based on this idea is called a “pseudo-pass function.” The “pseudo-pass function” stands for a function, in which “pass status” is output as a status even though bit errors are occurring within an extent that they can be corrected by the aforementioned ECC such as 1 bit, 2 bit, in the result of the read-out for verification. The “pseudo-pass function”, for example, is described in the U.S. Pat. No. 6,185,134. According to the pseudo-pass function, if a number of failures (bit errors) are within an extent correctable by the ECC, there is no hindrance in the quality of the non-volatile semiconductor memory device. Further the non-volatile semiconductor memory device may include memory cells whose data programming speed is slower than other memory cells. In a case that a number of memory cells whose data programming speed id slow and are of a number within the extent of being correctable by ECC, data programming of the non-volatile semiconductor memory device may be completed without waiting for completion of data programming of all the memory cells. As a consequence, the programming time of the non-volatile semiconductor memory device may be shortened.
However, in a non-volatile semiconductor memory device having the pseudo-pass function, if the number of bit errors are beyond the number of bits which are acceptable to the pseudo-pass function, there exists a problem that the accumulation time of the bit scan becomes longer because the bit scan is repeated until the number of bit scans approaches a predetermined regulation time.
The present invention assigns to provide a non-volatile semiconductor memory device, by which the accumulation time of the bit scan can be reduced, and a non-volatile memory system therewith.